Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components, such as transistors comprising gates and source/drain regions, are formed in very large numbers on the substrate surface by depositing layers of material on the substrate and/or implanting impurities in the substrate. The circuit components are interconnected locally and globally by several patterned metal layers interleaved with dielectric layers formed above and extending substantially horizontally with respect to the substrate surface. Many identical devices are usually formed on the same substrate, which is typically in the form of a substantially circular thin wafer of silicon.
The individual circuit components and interconnections are conventionally formed using photolithographic techniques. Typically, a photosensitive material, known as a photoresist, is applied to a substrate surface, a patterned mask is placed in a machine known as a "stepper", and light is impinged on the photoresist layer through the mask at a particular part of the substrate to form a latent image of the pattern. The patterned mask allows light to impinge only on selected areas of the photoresist-coated substrate, thus transferring the mask's pattern to the photoresist, which is subsequently developed to form a photoresist mask through which the substrate surface is etched or implanted with impurities as necessary.
The mask and the substrate are conventionally first aligned by the stepper using a set (or sets) of global alignment marks typically located near an edge of the substrate surface, isolated from other features on the surface. A typical set of alignment marks is depicted in FIGS. 1a and 1b, and comprises a set of trenches 2, called field (or field oxide) areas, etched in the substrate 1, while active areas are designated by reference numeral 3. The trenches 2 are spaced apart distances of about 8 .mu.m and have a depth d of about 1200 .ANG., a width w of about 8.mu., and a length 1 of about 50 .mu.m. The alignment marks provide an interference fringe to which the stepper can align. The stepper illuminates the marks and the reflected light signal produced by the marks is read by the stepper to obtain the requisite precise alignment.
The global alignment marks are used many times during the fabrication of devices on the substrate surface, i.e., every time a mask is employed, the global alignment marks are initially used to align the stepper. A plurality of layers are deposited on the substrate over the alignment marks during processing, thereby obscuring the marks resulting in the generation of a progressively weaker signal to the stepper. Specifically, as depicted in FIG. 2, layers 3, 4, 5 deposited on top of the alignment marks tend to have uneven upper surfaces. For example, steps R occur in layers 3, 4, 5, at the edges of trenches 2, which lead to distortion of the light from the stepper and the signal reflected from the alignment marks, thereby decreasing the accuracy of stepper global alignment which, in turn, leads to failure of the finished device. This problem leads to an undesirable decrease in manufacturing throughput and increased production costs.
There exists a need for a stepper global alignment structure wherein the global alignment mark's ability to transmit a strong and accurate signal to the stepper is maintained throughout wafer processing.